1. Field of the Invention
The invention relates to a dynamic random access memory (DRAM) using the capacitance of the gate of a MOS field effect transistor (MOSFET).
2. Description of the Related Art
FIG. 2 is a circuit diagram which shows a typical arrangement of memory cells and a sense amplifier circuit in a conventional DRAM.
The DRAM of FIG. 2 employs complementary MOS (CMOS) technology and has intersecting pairs of complementary bit lines BL1, BL2 and word lines WL1, WL2, to which memory cells 10 are connected. Memory cells 10 are depicted in FIG. 2 as two dynamic memory cells 11, 12, corresponding to two memory bits.
Each of the memory cells 11, 12 is composed of a charge transfer n-channel (N-type) enhancement mode MOSFET transistor (hereinafter "NMOS transistor"), identified respectively by reference numerals 11a, 12a. Each of the NMOS transistors has a drain and a gate which are connected, respectively, to the bit lines BL1, BL2 and the word lines WL1, WL2, and capacitors 11b, 12b which are connected, respectively, between the sources of the NMOS transistors 11a, 12a and a line carrying an internally generated equalizing potential VP.
The bit line BL1 is connected to a first node N21 through a first transfer gate, such as a NMOS transistor 21. Likewise, the bit line BL2 is connected to a second node N22 through a second transfer gate, such as NMOS transistor 22. NMOS transistors 21,22 are controlled by a transfer signal TG. A sense amplifier circuit 30 and a sense amplifier equalizing circuit 40 are connected between the first and second nodes N21, N22, which nodes may be considered to be common to the equalizing circuit 40.
The sense amplifier circuit 30 includes a N-type sense amplifier 30N which, when activated by a first active signal PL1, detects and amplifies a potential difference existing between the first and second nodes N21, N22 when the potential on the node N21 exceeds the potential on node N22. Sense amplifier circuit 30 also includes a P-type sense amplifier 30P which, when activated by a second active signal PL2, detects and amplifies a potential difference existing between the nodes when the potential on the node N22 exceeds the potential on node N21. The N-type sense amplifier 30N comprises two NMOS transistors 31,32. The sources of NMOS transistors 31,32 are both connected to the first active signal PL1, while the drains and gates of NMOS transistors 31,32 are cross-connected between the first and second nodes N21, N22. The P-type sense amplifier 30P comprises two p-channel (P-type) enhancement mode MOSFET transistors (hereinafter "PMOS transistors"), identified respectively by reference numerals 33, 34. The sources of PMOS transistors 33, 34 are both connected to the second active signal PL2, while the drains and gates of PMOS transistors 33, 34 are cross-connected between the first and second nodes N21, N22.
The sense amplifier equalizing circuit 40, when activated by a first equalization signal EQ1, sets the potential on the first and second nodes N21, N22 to an equalizing potential VP. The equalizing circuit 40 is composed of NMOS transistors 41,42, 43, all of which are gate-controlled by the first equalization signal EQ1. The drains of the NMOS transistors 41,42 are connected, respectively, to the first and second nodes N21, N22. The drain and source of the NMOS transistor 43 are also respectively connected to the nodes N21 and N22.
FIG. 3 is a waveform diagram useful for understanding operation of the circuitry shown in FIG. 2.
In this example, the equalizing potential VP is an internally generated voltage level of 1/2.Vcc, where Vcc is an external power source potential. As shown in FIG. 3, the transfer signal TG has a level higher than Vcc+Vth, where Vth is the gate threshold level of NMOS transistors 21 and 22. Therefore, these transfer gates 21 and 22 are conducting.
To reset the DRAM, the level of the equalization signal EQ1 is set to Vcc, the potential on the word lines WL1, WL2 is set to ground level, and the levels of the first and second active signals PL1, PL2 are set to 1/2. The equalizing potential VP (=1/2.Vcc) therefore is applied to the nodes N21, N22, through the conducting NMOS transistors 41,42 of the equalizing circuit 40. Further, the bit lines BL1, BL2 are connected to the nodes N21, N22, respectively, through the conducting NMOS transistors 21,22, so that the bit lines also have a potential of 1/2.Vcc.
The read-out and refresh operations for the memory cell 11, when it holds a data value, for example, a logic level "1" (corresponding to when the node N11 is at the level of Vcc), will now be described.
For the read-out operation, the level of the equalization signal EQ1 is set to the ground level, such that NMOS transistors 41,42, 43 of the equalizing circuit 40 are turned off. The potential on the word line WL1 is shifted from the ground level to a level higher than Vcc+Vth, thus connecting the node N11 to the bit line BL1, through the NMOS transistor 11a of the memory cell 11. In response, a redistribution of charge occurs, based on the capacitance 11b and the capacitance of the bit line BL1. As a result, the potential of the bit line BL1 rises from 1/2.Vcc to 1/2.Vcc+.alpha.. The potential on the bit line BL2 remains at 1/2.Vcc. Accordingly, the potential on the node N21 is shifted to 1/2.Vcc+.alpha., through the conducting transfer gate NMOS transistor 21, while the potential on the node N22 remains at the level of 1/2.Vcc.
Next, the level of the first active signal PL1 is shifted from 1/2.Vcc to ground level, while the level of the second active signal PL2 is shifted from 1/2.Vcc to Vcc, thereby activating the sense amplifier circuit 30. When the sense amplifier circuit 30 is activated, the potential on the node N21 is shifted from the 1/2.Vcc+.alpha. level to the Vcc level, and the potential on the node 22 is shifted from 1/2.Vcc to the ground level. As a result, the potential on the bit line BL1 is shifted from the 1/2.Vcc+.alpha. level to the Vcc level, through the conducting NMOS transistor 21, and the potential on the bit line BL2 is shifted from 1/2.Vcc to the ground level, through the conducting NMOS transistor 22. Throughout this operation, the transfer signal TG is maintained at a level higher than Vcc+Vth, so that NMOS transistors 21 and 22 conduct, and the potential on the bit lines BL1 and BL2 can be shifted to Vcc and ground, respectively.
Thereafter, the nodes N21, N22, or the bit lines BL1, BL2, are connected to a pair of data busses (not shown), by an output from a column decoder (not shown), and the stored data is outputted externally to complete the read-out operation. Further, since the potential on the word line WL1 is set to a level higher than Vcc+Vth, NMOS transistor 11 a of the memory cell 11 is turned on (conductive). As a result, the potential on the node N11 returns to the Vcc level (the level on the bit line BL1), thus completing the refresh operation.
FIG. 4 is a circuit diagram illustrating memory cells and sense amplifier circuits in another conventional DRAM, wherein reference characters common to those in FIG. 2 designate the same elements.
In the DRAM of FIG. 4, instead of the sense amplifier equalizing circuit 40, a bit line equalizing circuit 50 is connected between the bit lines BL1, BL2. This equalizing circuit 50, when activated by a second equalization signal EQ2, sets the potential on the bit lines BL1, BL2 to the equalizing potential VP. The bit line equalizing circuit 50 is composed of NMOS transistors 51, 52, 53, all of which are gate-controlled by the equalization signal EQ2. The sources of the NMOS transistors 51, 52 are connected commonly to the equalizing potential VP. The drains of the NMOS transistors 51,52 are connected, respectively, to the bit lines BL1, BL2. The drain and source of NMOS transistor 53 are also respectively connected to the bit lines BL1, BL2.
The DRAM shown in FIG. 4 performs read-out and refresh operations which are similar to those performed by the circuitry shown in FIG. 2, except for equalization. The equalizing operation performed when resetting the DRAM in FIG. 4 has an order different from that of the corresponding operation for the DRAM shown in FIG. 2. That is, for equalization of the potentials on the bit lines BL1, BL2 and the nodes N21, N22, of the circuit shown in FIG. 4, first the level of the equalization signal EQ2 is shifted to Vcc, so that all of NMOS transistors 51, 52, 53 of the equalizing circuit 50 are turned on. As a result, the potential on the bit lines BL1, BL2 is shifted to 1/2.Vcc, through the NMOS transistors 51,52, 53. Then, the potential on the nodes N21, N22 is shifted to the 1/2.Vcc level, through the NMOS transistors 21,22.
However, the above-described DRAM's have encountered the following problems:
(i) Since the NMOS transistors 21,22, which are controlled by the transfer signal TG, are provided between the bit line BL1 and the node N21, and between the bit line BL2 and the node 22, respectively, a delay occurs in equalizing the potentials of all of the bit lines BL1, BL2 and the nodes N21, N22, to 1/2.Vcc;
(ii) The transfer signal TG requires a potential higher than Vcc+Vth for refreshing the memory cells 11, 12. This potential is higher than the external source potential Vcc, and accordingly, can be obtained through bootstrap operation by capacitance feed-back. However, the level of the thus obtained transfer signal TG floats, so that if the level is lowered unintentionally, as by a short-circuit or leakage due to a defect produced during manufacture of the DRAM, the equalizing operation for the nodes N21, N22 would be insufficient, resulting in erroneous operation of the DRAM.